application note printed in japan 78k/0 series 8-bit single-chip microcontrollers basics (ii) m PD78044F subseries m pd78044h subseries m pd780208 subseries m pd780228 subseries document no. u10121ej3v0an00 (3rd edition) date published august 1997 j 1993
summary of contents chapter 1 overview ....................................................................................................................... 1 chapter 2 software basics ....................................................................................................... 15 chapter 3 system clock switching application .............................................................. 37 chapter 4 watchdog timer application ............................................................................... 51 chapter 5 16-bit timer/event counter application ......................................................... 59 chapter 6 8-bit timer/event counter application ........................................................... 101 chapter 7 watch timer application ....................................................................................... 117 chapter 8 serial interface application ............................................................................. 127 chapter 9 a/d converter application ................................................................................... 215 chapter 10 applications of fip controller/driver ......................................................... 249 chapter 11 applications of 6-bit up/down counter .......................................................... 275 appendix a spd chart description ............................................................................................ 281 appendix b revision history ......................................................................................................... 289
fip is a trademark of nec corporation. eeprom and iebus are trademarks of nec corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96. 5
nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
major changes page description throughout the following products have been added as applicable products: m PD78044F, m pd78044h, and m pd780228 subseries, m pd780206, and m pd780208 the following subseries have been dropped as applicable products: m pd78024 and m pd78044a subseries p.37, 38 the following register formats and tables are described separately according to the p.39, 40 products: p.53, 54 tables 3-1 and 3-2 , figures 3-1 , 3-2 , 4-2 , 4-3 , 8-1 , 8-2 , 9-1 , 9-2 , 10-7 , and 10-8 p.128, 129 p.216, 217 p.258, 260 p.1 the following subseries have been added in section 1.1 . m pd78075b, m pd78075by, m pd780018, m pd780018y, m pd780058, m pd780058y, m pd78058f, m pd78058fy, m pd780034, m pd780034y, m pd780024, m pd780024y, m pd78014h, m pd780964, m pd780924, m pd780228, m pd78044h, m PD78044F, m pd780308, m pd780308y, m pd78064b, m pd78098b, m pd780973, m pd780805 subseries, and m pd78p0914 p.40 table 3-3 has been added. p.53 note 2 and caution 2 have been added to figure 4-2 . p.55 figure 4-4 has been added. p.63 a caution has been added to figure 5-5 . p.127 table 8-2 has been added. p.130 note 4 and a caution have been added to figure 8-3 . p.139 a caution has been added to figure 8-9 . p.141 section 8.1 the m pd6252 has been defined as a product for maintenance purposes only. p.219 figure 9-4 has been added. the mark shows major revised points.
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preface target users this application note is for engineers who wish to understand 78k/0 series devices and design application programs using these devices. ? target products in each subseries m PD78044F subseries : m pd78042f, m pd78043f, m PD78044F, m pd78045f, m pd78p048a m pd78044h subseries : m pd78044h, m pd78045h, m pd78046h, m pd78p048b note m pd780208 subseries : m pd780204, m pd780205, m pd780206, m pd780208, m pd78p0208 m pd780228 subseries : m pd780226 note , m pd780228 note , m pd78f0228 note note under development objective the purpose of this application note is to use program examples to help users to understand the basic functions of 78k/0 series devices. the program and hardware structures published here are illustrative examples and are not designed for mass production. organization this application note is broadly divided into the following areas. ? overview ? software ? hardware *
the following application notes are supported. document name document no. applicable subseries description japanese english 78k/0 series application iea-715 iea-1288 m pd78002, 78002y describes basic functions of 78k/0 note, basics (i) m pd78014, 78014y series products, using program m pd78018f, 78018fy examples. 78k/0 series application u10121j this m PD78044F note, basics (ii) manual m pd78044h m pd780208 m pd780228 78k/0 series application iea-767 u10182e m pd78054, 78054y note, basics (iii) m pd78064, 78064y m pd78078, 78078y m pd78083 m pd78098 78k/0 series application iea-718 iea-1289 all subseries of 78k/0 series describes the floating-point note, floating-point operation except for m pd78002 and operation application programs of program m pd78002y subseries 78k/0 series products. m pd78014 series application iea-744 iea-1301 m pd78014 describes the functions and note, electronic notes only the m pd78014 and configuration of electronic notes, m pd78p014 are applicable. using m pd78014 subseries products as examples. caution in this application note, the application examples and program listings are written for the main system clock operating at 4.19 mhz. they are not for the main system clock operating at 5.0 mhz.
reading this note this application note is for 78k/0 series products, but each subseries has different functions. each subseries is described in the chapters listed in the following table. sample applications for each subseries are given in those chapters indicated by circles. subseries m PD78044F m pd78044h m pd780208 m pd780228 chapter chapter 1 overview o o o o chapter 2 software basics o o o o chapter 3 system clock switching application o o o o chapter 4 watchdog timer application o o o o chapter 5 16-bit timer/event counter application o o o - chapter 6 8-bit timer/event counter application o o o - chapter 7 watch timer application o o o - chapter 8 serial interface application o o o - chapter 9 a/d converter application o o o o chapter 10 applications of fip controller/driver o o o o chapter 11 applications of 6-bit up/down counter o - - - legend significance of the : the left side is high-order data and data description the right side is low-order data. active-low description : xxx (line above pin and signal names) note : explanation of the note attached to the text. caution : contents that should be read carefully remark : supplemental explanation of the text number descriptions : binary numbers ............. xxxx or xxxxb decimal numbers .......... xxxx hexadecimal numbers .. xxxxh application area ? consumer product field
related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? common documents document name document number japanese english 78k/0 series application note, basics (ii) u10121j this manual 78k/0 series user's manual, instruction u12326j ieu-1372 78k/0 series instruction set u10904j - 78k/0 series instruction table u10903j - ? documents for m PD78044F subseries document name document number japanese english m pd78042f, 78043f, 78044f, 78045f data sheet u10700j u10700e m pd78p048a data sheet u10611j u10611e m PD78044F subseries user's manual u10908j u10908e m pd78044a, 78044f subseries special function register table u10701j - ? documents for m pd78044h subseries document name document number japanese english m pd78044h, 78045h, 78046h data sheet u10865j u10865e m pd78p048b data sheet to be created to be created m pd78044h subseries user's manual u11756j u11756e ? documents for m pd780208 subseries document name document number japanese english m pd780204, 780205, 780206, 780208 data sheet u10436j u10436e m pd78p0208 data sheet u11295j u11295e m pd780208 subseries user's manual u11302j u11302e m pd780208 subseries special function register table u10997j - *
documents for m pd780228 subseries document name document number japanese english m pd780226, 780228 data sheet u11797j u11797e m pd78f0228 preliminary product information u11971j u11971e m pd780228 subseries users manual u12012j u12012e the above documents may be revised without notice. use the latest versions when you design an application system. *
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- i - contents chapter 1 overview ....................................................................................................................... 1 1.1 78k/0 series product development ......................................................... 1 1.2 78k/0 series features .................................................................................... 3 chapter 2 software basics ....................................................................................................... 15 2.1 data transfer ................................................................................................... 15 2.2 data comparison .............................................................................................. 16 2.3 decimal addition .............................................................................................. 17 2.4 decimal subtraction ...................................................................................... 24 2.5 binary-to-decimal conversion .................................................................. 26 2.6 bit operation manipulation instruction .............................................. 28 2.7 binary multiplication (16 bits x 16 bits) .................................................. 29 2.8 binary division (32 bits/16 bits) ................................................................... 33 chapter 3 system clock switching application .............................................................. 37 3.1 switching pcc after reset ......................................................................... 46 3.2 switching during power on/off ............................................................... 47 chapter 4 watchdog timer application ............................................................................... 51 4.1 setting the watchdog timer mode ......................................................... 56 4.2 interval timer mode setting ...................................................................... 58 chapter 5 16-bit timer/event counter application ......................................................... 59 5.1 interval timer setting .................................................................................. 65 5.2 pwm output ........................................................................................................ 67 5.3 remote control reception ........................................................................ 69 5.3.1 remote control reception by a counter clear ........................................ 72 5.3.2 remote control reception by pwm output and free running .............. 86
- ii - chapter 6 8-bit timer/event counter application ........................................................... 101 6.1 setting the interval timer ......................................................................... 106 6.1.1 setting an 8-bit timer ................................................................................ 107 6.1.2 setting the 16-bit timer ............................................................................. 109 6.2 musical scale generation ........................................................................... 111 chapter 7 watch timer application ....................................................................................... 117 7.1 watch and led display program .............................................................. 119 chapter 8 serial interface application ............................................................................. 127 8.1 interfacing with eeprom tm ( m pd6252) ...................................................... 141 8.1.1 communication in the 2-wire serial i/o mode ......................................... 143 8.2 interfacing with the osd lsi ( m pd6451a) ................................................ 153 8.3 sbi mode interface ......................................................................................... 158 8.3.1 application as a master cpu .................................................................... 160 8.3.2 application as a slave cpu ....................................................................... 169 8.4 3-wire serial i/o mode interface .............................................................. 173 8.4.1 application as a master cpu .................................................................... 174 8.4.2 application as a slave cpu ....................................................................... 178 8.5 half-duplex asynchronous communication ....................................... 182 8.5.1 half-duplex asynchronous communication of the 3-wire mode ............. 182 8.5.2 half-duplex asynchronous communication in the sbi mode .................. 197 chapter 9 a/d converter application ................................................................................... 215 9.1 level meter ........................................................................................................ 220 9.2 thermometer ..................................................................................................... 229 9.3 analog key input .............................................................................................. 239 9.4 4-channel input a/d conversion ............................................................... 245 chapter 10 applications of fip controller/driver ......................................................... 249 10.1 12-digit display for fip and key input .................................................... 262 10.1.1 12-digit fip display ................................................................................... 263 10.1.2 key input .................................................................................................... 266 10.1.3 description of package .............................................................................. 268 10.1.4 example of use .......................................................................................... 270 10.1.5 spd chart .................................................................................................. 272 10.1.6 program listing .......................................................................................... 273
- iii - chapter 11 applications of 6-bit up/down counter ......................................................... 275 11.1 1-second counter ........................................................................................... 277 appendix a spd chart description ........................................................................................... 281 appendix b revision history ........................................................................................................ 289
- iv - list of figures (1/4) figure no. title page 1-1. block diagram of the m PD78044F subseries .................................................................. 4 1-2. block diagram of the m pd78044h subseries .................................................................. 7 1-3. block diagram of the m pd780208 subseries .................................................................. 10 1-4. block diagram of the m pd780228 subseries .................................................................. 13 2-1. data exchange .................................................................................................................. 15 2-2. data comparison .............................................................................................................. 16 2-3. decimal addition ............................................................................................................... 17 2-4. decimal subtraction .......................................................................................................... 24 2-5. binary-to-decimal conversion .......................................................................................... 26 2-6. bit operation ...................................................................................................................... 28 2-7. binary multiplication .......................................................................................................... 29 2-8. binary division ................................................................................................................... 33 3-1. format of the processor clock control register ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 39 3-2. format of the processor clock control register ( m pd780228 subseries) .................... 40 3-3. format of the display mode register 0 ( m PD78044F and m pd78044h subseries) ...... 41 3-4. format of the display mode register 0 ( m pd780208 subseries) ................................... 42 3-5. format of the display mode register 1 ( m PD78044F and m pd78044h subseries) ...... 44 3-6. format of the display mode register 1 ( m pd780208 subseries) ................................... 45 3-7. cpu clock switching after reset ( m PD78044F subseries) ......................................... 46 3-8. example of the system clock switching circuit .............................................................. 47 3-9. system clock switching during power on and off ( m PD78044F subseries) ................ 48 4-1. format of timer clock selection register 2 ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 52 4-2. format of the watchdog timer mode register ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 53 4-3. format of the watchdog timer mode register ( m pd780228 subseries) ....................... 54 4-4. format of the watchdog timer clock selection register (only for the m pd780228 subseries) ............................................................................... 55 4-5. count timing of the watchdog timer .............................................................................. 58 5-1. format of timer clock selection register 0 .................................................................... 60 5-2. format of the 16-bit timer mode control register ......................................................... 61
- v - list of figures (2/4) figure no. title page 5-3. format of the 16-bit timer output control register ....................................................... 62 5-4. format of the port mode register 3 ................................................................................. 63 5-5. format of the external interrupt mode register .............................................................. 63 5-6. format of the sampling clock selection register ........................................................... 64 5-7. example of the remote control receiving circuit .......................................................... 69 5-8. ic output signal for remote control transmission ........................................................ 70 5-9. output signal of the receiving preamplifier .................................................................... 71 5-10. sampling the remote control signal ............................................................................... 72 6-1. format of timer clock selection register 1 .................................................................... 102 6-2. format of the 8-bit timer mode control register ........................................................... 103 6-3. format of the 8-bit timer output control register ......................................................... 104 6-4. format of port mode register 3 ....................................................................................... 105 6-5. count timing of an 8-bit timer ........................................................................................ 106 6-6. musical scale generation circuit ..................................................................................... 111 6-7. timer output and interval ................................................................................................. 111 7-1. format of timer clock selection register 2 .................................................................... 117 7-2. format of the watch timer mode control register ........................................................ 118 7-3. schematic of watch data ................................................................................................. 119 7-4. led display timing ........................................................................................................... 120 7-5. example circuit of the watch timer ................................................................................ 120 8-1. format of timer clock selection register 3 ( m PD78044F and m pd780208 subseries) ........................................................................ 128 8-2. format of timer clock selection register 3 ( m pd78044h subseries) .......................... 129 8-3. format of serial operating mode register 0 (only for the m PD78044F and m pd780208 subseries) ................................................... 130 8-4. format of the serial operating mode register 1 ............................................................ ( m PD78044F and m pd780208 subseries) ........................................................................ 132 8-5. format of the serial operating mode register 1 ( m pd78044h subseries) ................... 133 8-6. format of the interrupt timing setting register (only for the m PD78044F and m d780208 subseries) ...................................................... 134 8-7. format of the serial bus interface control register (only for the m PD78044F and m pd780208 subseries) ................................................... 135 8-8. format of the automatic data transmit/receive control register (only for the m PD78044F and m pd780208 subseries) ................................................... 137
- vi - list of figures (3/4) figure no. title page 8-9. format of the automatic data transmit/receive interval setting register (only for the m PD78044F and m pd780208 subseries) ................................................... 138 8-10. m pd6252 pin configuration .............................................................................................. 141 8-11. m pd6252 connection example ......................................................................................... 143 8-12. m pd6252 communication format .................................................................................... 145 8-13. connection example with m pd6451a .............................................................................. 153 8-14. m pd6451a communication format .................................................................................. 153 8-15. connection example of the sbi mode ............................................................................. 158 8-16. sbi mode communication format ................................................................................... 159 8-17. timed out ack signal ...................................................................................................... 160 8-18. bus line test .................................................................................................................... 160 8-19. connection example of the 3-wire serial i/o mode ....................................................... 173 8-20. communication format of the 3-wire serial i/o mode ................................................... 173 8-21. busy signal output ........................................................................................................... 178 8-22. system structure (3-wire mode) ...................................................................................... 182 8-23. 3-wire mode transmission format .................................................................................. 183 8-24. 3-wire mode reception format ....................................................................................... 184 8-25. system structure (sbi mode) ........................................................................................... 197 8-26. sbi mode transmission format ....................................................................................... 198 8-27. sbi mode reception format ............................................................................................ 199 9-1. format of the a/d converter mode register ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 216 9-2. format of the a/d converter mode register ( m pd780228 subseries) .......................... 217 9-3. format of the a/d converter input selection register ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 218 9-4. format of the analog input channel specification register (only for the m pd780228 subseries) ............................................................................... 219 9-5. level meter circuit example ............................................................................................. 220 9-6. a/d conversion result and led display ......................................................................... 220 9-7. conceptual diagram of the peak hold ............................................................................. 221 9-8. thermometer circuit example .......................................................................................... 229 9-9. temperature and output characteristics ......................................................................... 230 9-10. analog key input circuit example .................................................................................... 240 9-11. timing chart in the 4-channel scanning mode ............................................................... 245
- vii - list of figures (4/4) figure no. title page 10-1. format of display mode register 0 ( m PD78044F and m pd78044h subseries) ............ 251 10-2. format of display mode register 0 ( m pd780208 subseries) ......................................... 252 10-3. format of display mode register 0 ( m pd780228 subseries) ......................................... 254 10-4. format of display mode register 1 ( m PD78044F and m pd78044h subseries) ............ 255 10-5. format of display mode register 1 ( m pd780208 subseries) ......................................... 256 10-6. format of display mode register 1 ( m pd780228 subseries) ......................................... 257 10-7. format of display mode register 2 ( m pd780208 subseries) ......................................... 258 10-8. format of display mode register 2 ( m pd780228 subseries) ......................................... 260 10-9. fip controller operation timing ....................................................................................... 261 10-10. configuration of 12-digit fip display and key input ....................................................... 262 10-11. pin layout for 9-segment display .................................................................................... 264 10-12. relationship between contents of display data memory and segment output ........... 265 10-13. display example ................................................................................................................ 266 10-14. key interrupt timing chart ............................................................................................... 267 10-15. compensating for chattering ............................................................................................ 268 11-1. block diagram of 6-bit up/down counter ....................................................................... 275 11-2. format of 6-bit up/down counter control register ........................................................ 276
- viii - list of tables table no. title page 1-1. function overview of the m PD78044F subseries ............................................................ 5 1-2. function overview of the m pd78044h subseries ........................................................... 8 1-3. function overview of the m pd780208 subseries ............................................................ 11 1-4. function overview of the m pd780228 subseries ............................................................ 14 3-1. maximum time required to change the cpu clock ( m PD78044F, m pd78044h, and m pd780208 subseries) ................................................ 37 3-2. maximum time required to change the cpu clock ( m pd780228 subseries) ............. 38 3-3. relationship between the cpu clock and minimum instruction execution time .......... 40 5-1. valid time for input signal ............................................................................................... 72 5-2. valid time of the input signal .......................................................................................... 86 6-1. musical scale and frequencies ........................................................................................ 112 8-1. available serial interface channels in each subseries .................................................. 127 8-2. serial interface registers ................................................................................................. 127 8-3. description of m pd6252 pins ............................................................................................ 142 8-4. m pd6252 command list ................................................................................................... 144 8-5. sbi mode signal list ......................................................................................................... 159 9-1. a/d conversion values and temperatures ..................................................................... 231 9-2. input voltages and key codes ......................................................................................... 239 9-3. resistances of r1 to r15 ................................................................................................. 240 10-1. differences between m PD78044F, m pd78044h, m pd780208, and m pd780228 subseries ...................................................................................................... 250 a-1. comparison of spd symbols and flowcharts ................................................................. 281
1 chapter 1 overview chapter 1 overview 1.1 78k/0 series product development the 78k/0 series products were developed as shown below. the subseries names are indicated in frames. note being planned * m pd78083 m PD78044F m pd78064 m pd78098 m pd78098b m pd78p0914 m pd780973 m pd78064b m pd780308 m pd78044h m pd780228 m pd780208 m pd780924 m pd780964 m pd78002 m pd780001 m pd78014 m pd78018f m pd78014h m pd780024 m pd780034 m pd78054 m pd78058f m pd780058 m m pd78070a m pd78078 m pd78075b m pd78002y m pd78064y m pd780308y m pd78014y m pd78018fy m pd780024y m pd780034y m pd78054y m pd78058fy m pd780058y note m pd780018ay m m m m m m m m m m m m m m m m m m m m m m m pd78070ay m pd78078y m pd78075by products currently being mass-produced products under development y subseries products are compatible with the i 2 c bus. used for control for inverter control for fip tm driving for lcd driving compatible with iebus tm for meter control for lv 100-pin 100-pin 100-pin 100-pin 100-pin 100-pin 100-pin 64-pin 80-pin 80-pin 100-pin 100-pin 80-pin 80-pin 80-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin emi noise-reduced versions of the pd78078 a timer has been added to the pd78054 to enhance its external interface functions. rom-less versions of the pd78078 the serial i/o of the pd78078y has been enhanced by limiting its functions serial i/o of the pd78054 has been enhanced. emi noise-reduced versions of the pd78054 emi noise-reduced versions of the pd78054 a uart and d/a converter have been added to the pd78014 to enhance its i/o. the a/d converter of the pd780024 has been enhanced. the serial i/o of the pd78018f has been enhanced. emi noise-reduced versions of the pd78018f. emi noise-reduced version of the pd78018f low-voltage (1.8 v) versions of the pd78014. rom and ram variations have been enhanced. an a/d converter and 16-bit timer have been added to the pd78002. an a/d converter has been added to the pd78002. basic subseries for control the i/o and the fip controller/driver of the PD78044F have been enhanced. total indication output pins: 53 the i/o and the fip controller/driver of the pd78044h have been enhanced. total indication output pins: 48 n-ch open-drain i/o pins have been added to the PD78044F. total indication output pins: 34 basic subseries for fip driving. total indication output pins: 34 sio of the pd78064 has been enhanced. rom and ram have been extended. emi noise-reduced version of the pd78064 emi noise-reduced version of the pd78098 an iebus controller has been added to the pd78054. this product includes a controller/driver for driving car meters. this product includes the pwm output, lv digital code decoder, and hsync counter. basic subseries for lcd driving. these products include a uart. an a/d converter of the pd780924 has been enhanced. this product includes an inverter control circuit and uart. emi noise-reduced version. this product includes a uart and can operate at a low voltage (1.8 v). 78k/0 series
2 78k/0 series application note the table below shows the main differences between subseries. function rom timer 8-bit 10-bit 8-bit minimum external serial interface i/o subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a v dd expansion m pd78075b 32k-40 k 4 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch (uart: 1 ch) 88 pins 1.8 v o m pd78078 48k-60k m pd78070a - 61 pins 2.7 v m pd780058 24k-60k 2 ch 2 ch 3ch (time-multiplexing 68 pins 1.8 v uart: 1ch) m pd78058f 48k-60k 3 ch (uart: 1 ch) 69 pins 2.7 v m pd78054 16k-60k 2.0 v m pd780034 8k-32k - 8 ch - 51 pins 1.8 v m pd780024 8 ch - m pd78014h 2 ch 53 pins m pd78018f 8k-60k m pd78014 8k-32k 2.7 v m pd780001 8k - - 1 ch 39 pins - m pd78002 8k-16k 1 ch - 53 pins o m pd78083 - 8 ch 1 ch (uart: 1 ch) 33 pins 1.8 v - m pd780964 8k-32k 3 ch note - 1 ch - 8 ch - 2 ch (uart: 2 ch) 47 pins 2.7 v o m pd780924 8 ch - m pd780208 32k-60k 2 ch 1 ch 1 ch 1 ch 8 ch - - 2 ch 74 pins 2.7 v - m pd780228 48k-60k 3 ch - - 1 ch 72 pins 4.5 v m pd78044h 32k-48k 2 ch 1 ch 1 ch 68 pins 2.7 v m PD78044F 16k-40k 2 ch m pd780308 48k-60k 2 ch 1 ch 1 ch 1 ch 8 ch - - 3ch (time-multiplexing 57 pins 2.0 v - uart: 1ch) m pd78064b 32k 2 ch (uart: 1 ch) m pd78064 16k-32k m pd78098b 40k-60k 2 ch 1 ch 1 ch 1 ch 8 ch - 2 ch 3 ch (uart: 1 ch) 69 pins 2.7 v o m pd78098 32k-60k m pd780973 24k-32k 3 ch 1 ch 1 ch 1 ch 5 ch - - 2 ch (uart: 1 ch) 56 pins 4.5 v - m pd78p0914 32k 6 ch - - 1 ch 8 ch - - 2 ch 54 pins 4.5 v o note 10-bit timer: 1 channel for control for inverter control for fip driving for lcd driving compatible with iebus for meter control for lv 3 ch (uart: 1 ch, time- multiplexing 3-wire: 1ch)
3 chapter 1 overview 1.2 78k/0 series features the 78k/0 series devices are 8-bit single-chip microcontrollers ideally suited for applications in the consumer field. the m PD78044F subseries are devices that implement high-speed, high-performance cpus and have on-chip peripheral hardware, such as rom, ram, i/o ports, timers, serial interfaces, a/d converter, fip controller/driver, 6-bit up/down counter, and interrupt controllers. the m pd78044h subseries of devices has been implemented by adding n-ch open-drain i/o pins to the m PD78044F subseries. the m pd780208 subseries has an enhanced version of the fip controller/driver of the m PD78044F subseries. the m pd780228 subseries has an enhanced version of the fip controller/driver of the m pd78044h subseries. the one-time prom or eprom versions or flash memory version, that can operate at the same low voltage as mask rom versions, such as the m pd78p048a, m pd78p048b, m pd78p0208, and m pd78f0228 are also provided. these products are well suited for fast shift to production of application systems and small-lot production. a block diagram and an overview of the functions of each subseries are shown on the following pages. * * *
4 78k/0 series application note figure 1-1. block diagram of the m PD78044F subseries to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 ci0/intp3/p03 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/ti0/p00- intp3/ci0/p03 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter1 8-bit timer/ event counter2 watchdog timer watch timer 6-bit up/down counter serial interface 0 serial interface 1 a/d converter interrupt control buzzer output clock output control v dd v ss ic (v pp ) ram 78k/0 cpu core rom port0 port2 port3 port7 port8 port9 port10 port12 fip controller/ driver system control p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p70-p74 p80, p81 p90-p97 p100-p107 p110-p117 p120-p127 fip0-fip33 v load reset x1 x2 xt1/p04 xt2 port1 port11 remarks 1. the capacities of the internal rom and ram differ depending on the product. 2. the value enclosed in parentheses is applied to the m pd78p048a.
5 chapter 1 overview table 1-1. function overview of the m PD78044F subseries (1/2) product name m pd78042f m pd78043f m PD78044F m pd78045f m pd78p048a item rom masked rom one-time prom/eprom 16k bytes 24k bytes 32k bytes 40k bytes 60k bytes note 1 high-speed ram 512 bytes 1024 bytes 1024 bytes note 2 extended ram - 1024 bytes buffer ram 64 bytes fip display ram 48 bytes general-purpose registers 8 bits x 8 x 4 banks for main system clock 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 5.0 mhz) for subsystem clock 122 m s (at 32.768 khz) instruction set ? 16-bit operations ? multiplication/division (8 bits x 8 bits, 16 bits/8 bits) ? bit (set, reset, test, boolean operations) ? bcd conversion, etc. i/o ports (including those ? total : 68 pins multiplexed with fip pins) ? cmos input : 2 pins ? cmos i/o : 27 pins ? n-ch open-drain i/o : 5 pins ? p-ch open-drain i/o : 16 pins ? p-ch open-drain output : 18 pins fip controller/driver ? total : 34 pins ? segments : 9 to 24 pins ? digits : 2 to 16 pins a/d converter ? 8-bit resolution x 8 channels ? power supply voltage: av dd = 4.0 to 6.0 v serial interface ? 3-wire serial i/o, sbi, or 2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel ? 6-bit up/down counter : 1 channel timer outputs 3 (one for 14-bit pwm output) notes 1. the memory size switching register (ims) can be used to select 16k, 24k, 32k, 40k, or 60k bytes. 2. the ims can be used to select 512k or 1024k bytes. minimum instruction execution time internal memory *
6 78k/0 series application note table 1-1. function overview of the m PD78044F subseries (2/2) product name m pd78042f m pd78043f m PD78044F m pd78045f m pd78p048a item clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz (at main system clock of 5.0 mhz) 32.768 khz (at subsystem clock of 32.768 khz) buzzer output 1.2 khz, 2.4 khz, 4.9 khz (at 5.0 mhz: main system clock) maskable internal: 10, external: 4 non-maskable internal: 1 software 1 test input internal: 1 power supply voltage v dd = 2.7 to 6.0 v package ? 80-pin plastic qfp (14 x 20 mm) ? 80-pin ceramic wqfn: only for the m pd78p048a vectored interrupt factors
7 chapter 1 overview figure 1-2. block diagram of the m pd78044h subseries to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 ci0/intp3/p03 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb note /p23 busy note /p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/ti0/p00- intp3/ci0/p03 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter1 8-bit timer/ event counter2 watchdog timer watch timer 6-bit up/down counter note serial interface 0 note serial interface 1 a/d converter interrupt control buzzer output clock output control v dd v ss ic (v pp ) ram 78k/0 cpu core rom port0 port2 port3 port7 port8 port9 port10 port12 fip controller/ driver system control p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p70-p74 p80, p81 p90-p97 p100-p107 p110-p117 p120-p127 fip0-fip33 v load reset x1 x2 xt1/p04 xt2 port1 port11 note only for the m pd78p048b remarks 1. the capacities of the internal rom and ram differ depending on the product. 2. the value enclosed in parentheses is applied to the m pd78p048b. *
8 78k/0 series application note table 1-2. function overview of the m pd78044h subseries (1/2) product name m pd78044h m pd78045h m pd78046h m pd78p048b note 1 item rom masked rom one-time prom/eprom 32k bytes 40k bytes 48k bytes 60k bytes note 2 high-speed ram 1024 bytes extended ram - 1024 bytes note 3 buffer ram - 64 bytes fip display ram 48 bytes general-purpose register 8 bits x 8 x 4 banks for main system clock 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 5.0 mhz) for subsystem clock 122 m s (at 32.768 khz) instruction set ? 16-bit operations ? multiplication/division (8 bits x 8 bits, 16 bits/8 bits) ? bit manipulations (set, reset, test, boolean operations) ? bcd conversion, etc. i/o ? total : 68 lines ports (including those multiplexed with fip pins) ? cmos input : 2 lines ? cmos i/o : 19 lines ? n-ch open-drain i/o : 13 lines ? p-ch open-drain i/o : 16 lines ? p-ch open-drain output : 18 lines fip controller/driver ? total : 34 lines ? segments: 9 to 24 lines ? digits : 2 to 16 lines a/d converter ? 8-bit resolution x 8 channels ? 8-bit resolution x 8 channels ? power supply voltage: av dd = 4.0 to 5.5 v ? power supply voltage: av dd = 4.0 to 6.0 v serial interface ? 3-wire serial i/o mode: 1 channel ? 3-wire serial i/o, sbi, or 2-wire serial i/o mode: 1 channel ? 3-wire serial i/o mode with automatic transmission/reception function: 1 channel notes 1. under development 2. the memory size switching register (ims) can be used to select 32k, 40k, 48k, or 60k bytes. 3. the internal extended ram size switching register (ixs) can be used to select 0 or 1024 bytes. internal memory minimum instruction execution time *
9 chapter 1 overview table 1-2. function overview of the m pd78044h subseries (2/2) product name m pd78044h m pd78045h m pd78046h m pd78p048b note item timer ? 16-bit timer/event counter : 1 channel ? 16-bit timer/event counter: ? 8-bit timer/event counter : 2 channels 1 channel ? watch timer : 1 channel ? 8-bit timer/event counter: ? watchdog timer : 1 channel 2 channels ? watch timer: 1 channel ? watchdog timer: 1 channel ? 6-bit up/down counter: 1 channel timer outputs 3 lines (one for 14-bit pwm output) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz (at main system clock of 5.0 mhz) 32.768 khz (at subsystem clock of 32.768 khz) buzzer output 1.2 khz, 2.4 khz, 4.9 khz (at main system clock of 5.0 mhz) maskable internal: 8, external: 4 internal: 10, external: 4 non-maskable internal: 1 software 1 test input internal: 1 power supply voltage v dd = 2.7 to 5.5 v v dd = 2.7 to 6.0 v package ? 80-pin plastic qfp (14 x 20 mm) ? 80-pin plastic qfp (14 x 20 mm) ? 80-pin ceramic wqfn note under development vectored interrupt factors
10 78k/0 series application note figure 1-3. block diagram of the m pd780208 subseries to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10- ani7/p17 av dd av ss av ref intp0/ti0/p00- intp3/p03 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/ event counter1 8-bit timer/ event counter2 watchdog timer watch timer serial interface 0 serial interface 1 a/d converter interrupt control buzzer output clock output control v dd v ss ic (v pp ) ram 78k/0 cpu core rom port0 port2 port3 port7 port8 port9 port10 port12 fip controller/ driver system control p00 p01-p03 p04 p10-p17 p20-p27 p30-p37 p70-p74 p80-p87 p90-p97 p100-p107 p110-p117 p120-p127 fip0-fip52 v load reset x1 x2 xt1/p04 xt2 port1 port11 remark 1. the capacities of the internal rom and ram differ depending on the product. 2. the value enclosed in parentheses is applied to the m pd78p0208.
11 chapter 1 overview table 1-3. function overview of the m pd780208 subseries (1/2) product name m pd780204 m pd780205 m pd780206 m pd780208 m pd78p0208 item rom masked rom one-time prom/eprom 32k bytes 40k bytes 48k bytes 60k bytes 60k bytes note 1 high-speed ram 1024 bytes extended ram - 1024 bytes 1024 bytes note 2 buffer ram 64 bytes fip display ram 80 bytes general-purpose registers 8 bits x 8 x 4 banks for main system clock 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 5.0 mhz) for subsystem clock 122 m s (at 32.768 khz) instruction set ? 16-bit operations ? multiplication/division (8 bits x 8 bits, 16 bits/8 bits) ? bit (set, reset, test, boolean operations) ? bcd conversion, etc. i/o ports (including those ? total : 74 pins multiplexed with fip pins) ? cmos input : 2 pins ? cmos i/o : 27 pins ? n-ch open-drain i/o : 5 pins ? p-ch open-drain i/o : 24 pins ? p-ch open-drain output : 16 pins fip controller/driver ? total : 53 pins ? segments : 9 to 40 pins ? digits : 2 to 16 pins a/d converter ? 8-bit resolution x 8 channels ? power supply voltage: av dd = 4.0 to 5.5 v serial interface ? 3-wire serial i/o, sbi, or 2-wire serial i/o mode selectable : 1 channel ? 3-wire mode (with automatic transmission/ reception function of up to 64 bytes) : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer outputs 3 (one for 14-bit pwm output) notes 1. the memory size switching register (ims) can be used to select 32k, 40k, 48k, or 60k bytes. 2. the internal extended ram size switching register (ixs) can be used to select either 0 or 1024 bytes. internal memory minimum instruction execution time *
12 78k/0 series application note table 1-3. function overview of the m pd780208 subseries (2/2) product name m pd780204 m pd780205 m pd780206 m pd780208 m pd78p0208 item clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz (at main system clock of 5.0 mhz) 32.768 khz (at subsystem clock of 32.768 khz) buzzer output 1.2 khz, 2.4 khz, 4.9 khz (at 5.0 mhz: main system clock) maskable internal: 9, external: 4 non-maskable internal: 1 software 1 text input internal: 1 power supply voltage v dd = 2.7 to 5.5 v package ? 100-pin plastic qfp (14 x 20 mm) ? 100-pin ceramic wqfn: only for the m pd78p0208 vectored interrupt factors
13 chapter 1 overview figure 1-4. block diagram of the m pd780228 subseries port0 p00, p01 p20-p25 port1 port2 port4 port5 port6 port7 port8 port9 port10 fip controller/ driver system control ti1/p23 tio50/p24 sck/p20 so/p21 si/p22 av dd ani0/p10- ani7/p17 av ss intp0/p00 intp1/p01 8-bit remote controller timer (tm1) 8-bit pwm timer (tm50) 78k/0 cpu core rom flash memory ram 1024 bytes v dd0 , v dd1 , v dd2 8-bit pwm timer (tm51) serial interface (sio3) a/d converter (a/d1) interrupt control (int) watchdog timer p40-p47 tio51/p25 p50-p57 p60-p67 p70-p77 p80-p87 p90-p97 p100-p107 fip0-fip47 v load reset x1 x2 p10-p17 v ss0 , v ss1 ic (v pp ) remarks 1. the internal rom capacity differs depending on the product. 2. the value in parentheses applies to the m pd78f0228 only. *
14 78k/0 series application note table 1-4. function overview of the m pd780228 subseries product name m pd780226 m pd780228 m pd78f0228 item rom masked rom flash memory 48k bytes 60k bytes 60k bytes note high-speed ram 1024 bytes extended ram 512 bytes fip display ram 96 bytes general-purpose registers 8 bits x 8 x 4 banks minimum instruction execution time 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at main system clock of 5.0 mhz) instruction set ? 16-bit operations ? multiplication/division (8 bits x 8 bits, 16 bits/8 bits) ? bit (set, reset, test, boolean operations) ? bcd conversion, etc. i/o ports (including those ? total : 72 pins multiplexed with fip pins) ? cmos input : 8 pins ? cmos i/o : 16 pins ? n-ch open-drain i/o : 16 pins ? p-ch open-drain i/o : 24 pins ? p-ch open-drain output : 8 pins fip controller/driver ? total : 48 pins ? 10-ma display current : 16 pins ? 3-ma display current : 32 pins a/d converter ? 8-bit resolution x 8 channels ? power supply voltage: av dd = 4.5 to 5.5 v serial interface ? 3-wire serial i/o mode: 1 channel timer ? 8-bit remote controller timer : 1 channel ? 8-bit pwm timer : 2 channels ? watchdog timer : 1 channel timer outputs 2 (8-bit pwm output enabled) maskable internal: 6, external: 4 non-maskable internal: 1 software 1 power supply voltage v dd = 4.5 to 5.5 v package 100-pin plastic qfp (14 x 20 mm) note the memory size switching register (ims) can be used to select 48k or 60k bytes. caution the m pd780228 subseries is under development. internal memory vectored interrupt factors *
15 chapter 2 software basics chapter 2 software basics 2.1 data transfer the addresses set in the de and hl registers are the first addresses used in data exchange. the number of bytes in the data exchange is specified in the b register. figure 2-1. data exchange de+b? de hl+b? hl address address data exchange (1) registers used a, b, de, hl (2) program listing exch: mov a,[de] xch a,[hl] xch a,[de] incw de incw hl dbnz b,$exch ret
16 78k/0 series application note 2.2 data comparison the addresses set in the de and hl registers are the first addresses used in data comparison. the number of bytes in the data comparison is specified in the b register. when the comparison result is equal, the cy flag is set to 0. when the result is not equal, cy is set to 1. after the flag setting, processing is returned to the main program. figure 2-2. data comparison de+b? de hl+b? hl address address data comparison (1) registers used a, b, de, hl (2) program listing comp: mov a,[de] cmp a,[hl] bnz $error incw de incw hl dbnz b,$comp clr1 cy br rtn error: set1 cy rtn: ret
17 chapter 2 software basics 2.3 decimal addition the lowest addresses for decimal addition are specified in the de and hl registers. the number of digits specified in bytnum are added. the addition result is saved in the area pointed to by the hl register. when the addition result is an overflow or an underflow, the processing branches to error processing. have the branch address defined as error in main program and make it a public declaration. figure 2-3. decimal addition de hl+ bytnum? hl hl hl+ bytnum? de+ bytnum? += address address address (1) flowchart bcdadd c number of bytes in the decimal addition b c? number of bytes in the decimal addition not including the sign do the augend and the addend have the same signs? no yes decimal addition ret decimal subtraction bcdad2
18 78k/0 series application note dadds cy 0 sign flag sflag 0 dadds1 a [de]+[hl]+cy add both the addend and augend to cy. de de+1, hl hl+1 increment the addend and augend addresses. b b? b=0 no yes a [de]+[hl]+cy add both the addend and augend to cy. cy=1 yes no sign flag sflag 1 cy=0 dadds3 decimal-adjust the result. cy=1 a7=1 no yes no yes yes no sign flag sflag=1 a7 1 dadds6 save a in memory ret error the result is decimal-adjusted and saved in memory.
19 chapter 2 software basics dsubs1 ret dsubs make the subtrahend positive. sign flag 0 minuend<0 yes no make the subtrahend positive. sign flag 1 dsubs2 b c, cy 0 a [de] ?[hl] ?cy subtract cy from the minuend minus the subtrahend. de de+1, hl hl+1 increment the minuend and subtrahend addresses c c? c=0 the result is decimal-adjusted and saved in memory. no yes cy=1 invert the sign flag by taking the 10's complement. result=0 yes no no yes dsubs5 yes no sign flag=1 assign a negative sign to the result.
20 78k/0 series application note (2) registers used ax, bc, de, hl (3) program listing ;************************************************************ ; * ; input parameters * ; hl register: start address of the addend * ; de register: start address of the augend * ; output parameters * ; hl register: start address of the operation result * ; * ;************************************************************ public bcdadd,bcdad1,bcdad2 public dadds public dsubs extrn error ; branch address for error processing extbit sflag ; sign flag ; bytnum equ 4 ; set the number of operand digits ; cseg bcdadd: mov c,#bytnum ; set the number of operand digits in the c register. bcdad1: mov a,c mov b,a dec b bcdad2: mov a,[hl+bytnum-1] ; read in the most significant bit (sign data) of the augend xchw ax,de xchw ax,hl xchw ax,de xor a,[hl+bytnum-1] ; read in the most significant bit (sign data) of the augend xchw ax,hl xchw ax,de xchw ax,hl bt a.7,$bcdad3 ; do the signs agree? else subtraction processing call !dadds ; then addition processing ret bcdad3: call !dsubs ret
21 chapter 2 software basics ;=========================================================== ; ***** decimal addition ***** ;=========================================================== dadds: clr1 cy clr1 sflag dadds1: mov a,[de] ; start addition from the least significant digit addc a,[hl] adjba mov [hl],a incw hl incw de dbnz b,$dadds1 ; end addition of (number-of-operand-digits C 1) mov a,[de] addc a,[hl] dadds2: bnc $dadds3 ; negative addition set1 sflag ; then set in the negative state clr1 cy dadds3: adjba bnc $dadds4 br error dadds4: bf a.7,$dadds5 br error dadds5: bf sflag,$dadds6 ; set sign set1 a.7 dadds6: mov [hl],a ret
22 78k/0 series application note ;================================================================= ; ***** decimal subtraction ***** ;================================================================= dsubs: push hl clr1 sflag mov a,[hl+bytnum-1] ; set the subtrahend to positive value. clr1 a.7 mov [hl+bytnum-1],a xchw ax,de xchw ax,hl xchw ax,de mov a,[hl+bytnum-1] bf a.7,$dsubs1 ; the minuend is negative. clr1 a.7 ; then set the minuend to a positive value. mov [hl+bytnum-1],a set1 sflag ; set the sign to negative. dsubs1: xchw ax,hl xchw ax,de xchw ax,hl mov a,c mov b,a clr1 cy dsubs2: mov a,[de] subc a,[hl] adjbs mov [hl],a incw hl incw de dbnz c,$dsubs2 ; end of the subtraction of the number of operand digits. bnc $dsubs5 ; then subtrahend > minuend pop hl push hl mov a,b mov c,a dsubs3: mov a,#99h ; complement operation on the subtraction result sub a,[hl] ; (subtraction-result C 99h) adjbs mov [hl],a incw hl dbnz c,$dsubs3 pop hl push hl set1 cy mov a,b mov c,a
23 chapter 2 software basics dsubs4: mov a,#0 ; add 1 to the complement operation result. addc a,[hl] adjba mov [hl],a incw hl dbnz c,$dsubs4 mov1 cy,sflag not1 cy mov1 sflag,cy ;==================================================== ; ***** 0 check of operation result ***** ;==================================================== dsubs5: mov a,b mov c,a pop hl push hl mov a,#0 dsubs6: cmp a,[hl] ; 0 check from the low-order digit incw hl bnz $dsubs7 dbnz c,$dsubs6 ; end of checking all digits for 0 pop hl ; then subtraction result = 0 ret dsubs7: bf sflag,$dsubs8 ; subtraction result is negative. pop hl ; then set sign push hl mov a,[hl+bytnum-1] set1 a.7 mov [hl+bytnum-1],a dsubs8: pop hl ret
24 78k/0 series application note 2.4 decimal subtraction the lowest addresses for decimal subtraction are set in the de and hl registers. subtraction is performed on the number of digits specified in bytnum. the subtraction result is saved in the area specified in the hl register. additionally, when the subtraction result is an overflow or an underflow, the processing branches to error processing. have the branch address defined as error in main program and make it a public declaration. this program replaces the augend and addend with the minuend and subtrahend respectively, and calls the decimal addition program. figure 2-4. decimal subtraction de hl bytnum? hl hl hl+ bytnum? de+ bytnum? ? address address address (1) flowchart bcdsub c number of bytes in the decimal subtraction the subtrahend and minuend act as the addend and augend in decimal addition. ret invert the sign bit of the subtrahend. (2) registers used ax, bc, de, hl
25 chapter 2 software basics (3) program listing ;************************************************************ ; input parameters * ; hl register: start address of the subtrahend * ; de register: start address of the minuend * ; output parameters * ; hl register: start address of the operation result * ; * ;************************************************************ public bytnum public bcdsub extrn bcdadd,bcdad2 ; bytnum equ 4 ; set the number of operand digits ; cseg bcdsub: mov c,#bytnum ; set the number of operand digits in the c register. bcdsu1: mov a,c mov b,a dec b mov a,[hl+bytnum-1] ; set the most significant bit (sign data) of the subtrahend for use in addition. mov1 cy,a.7 ; invert the sign data. not1 cy mov1 a.7,cy mov [hl+bytnum-1].a call !bcdad2 ; call decimal addition processing. ret
26 78k/0 series application note 2.5 binary-to-decimal conversion 16-bit binary data in the data memory is converted into 5-digit decimal data and saved in the data memory. the 16-bit binary data are divided by the decimal number 10 (4 times) and the conversion is based on the values of the results and remainders of these operations. figure 2-5. binary-to-decimal conversion xxxx 0x0x0x0x0x low high low high 16-bit binary (2 bytes) 5-digit decimal (5 bytes) example ffh is converted into decimal. ff00 0505020000 low high low high 16-bit binary (2 bytes) 5-digit decimal (5 bytes) (1) registers used ax, bc, hl
27 chapter 2 software basics (2) program listing public b_dconv datdec equ 10 dseg saddrp rega: ds 2 ; save 16-bit binary data. regb: ds 5 ; save 5-digit decimal data. column equ 4 b_dconv: movw ax,rega mov b,#colnum movw hl,#regb b_d1: mov c,#datdec divuw c xch a,c mov [hl],a incw hl xch a,c dbnz b,$b_d1 mov a,x mov [hl],a ret
28 78k/0 series application note 2.6 bit operation manipulation instruction the logical product (and) of the 1-bit flag in data memory and bit 4 in port 6 is taken. the logical sum (or) of the result and bit 5 of port 6 is output to bit 6 of port 6. figure 2-6. bit operation flg port6.4 port6.5 port6.6 (1) program listing public bit_op,flg bseg flg dbit bit_op: mov1 cy,flg and1 cy,p6.4 or1 cy,p6.5 mov1 p6.6,cy ret
29 chapter 2 software basics 2.7 binary multiplication (16 bits x 16 bits) the data in the multiplicand area (hikake; 16 bits) and the multiplier area (kake; 16 bits) are multiplied. the result is saved in the operation result storage area (kotae). figure 2-7. binary multiplication hikake + 1 hikake kake + 1 kake kotae + 3 kotae x operation result storage area (4 bytes) multiplier area (2 bytes) multiplicand area (2 bytes) = multiplication is implemented by adding the multiplicand only the number of 1 bits in the multiplier.
30 78k/0 series application note |
